Patent attributes
Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by:manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE);manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE;providing a tile structure (25; 26);providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); andexposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.
