US Patent 7149994 Integrated clock and input output placer

A method (200) of placing inputs, outputs, and clocks in a circuit design can include assigning (205) initial locations to inputs and outputs of the circuit design, selecting (210) at least one component type for the circuit design, and generating (215) a cost function having parameters corresponding to the selected component type. The method further can include annealing (220) the selected component type using the cost function and determining design constraints (225) for the selected component type according to the annealing step. The method can repeat to process additional component types such that design constraints determined for each additional component type do not violate design constraints determined for prior component types.