US Patent 7151679 Adaptive leading edge blanking circuit

An adaptive leading edge blanking circuit in which the leading edge blanking time is reduced at low to very low power levels of an SMPS, but is substantially constant at medium to high power levels. Adapted leading edge blanking time maybe provided by modifying a conventional leading edge blanking timer in which a fixed voltage reference source is replaced with a variable voltage reference source, the variable voltage reference being dependent upon power requirements on a secondary side of the SMPS.