US Patent 7154766 Ferroelectric memory

An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor, a sense amplifier connected to the bit line, and a block selector decoder which controls ON/OFF of the block selecting transistor. The timing for operating the sense amplifier and block selector decoder is changed corresponding to a position of a selected unit cell objective for data read of the plurality of unit cells.