US Patent 7154803 Redundancy scheme for a memory integrated circuit

A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line. A memory sector unusable status indicator element is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.