US Patent 7155361 Semiconductor test management system and method

A system and method for semiconductor test management. A second computer receives a scrap rule from a first computer, acquires an initial scrap threshold corresponding to the scrap rule, stores the scrap rule as a SBC/SBL (Statistic BIN Control/Statistic BIN Limit) rule when a scrap condition therein is less or equally restrictive than the initial scrap threshold, acquires a CP (Circuit Probing) test result for a wafer or wafer lot and generates an advisory report for the wafer or wafer lot by carrying the CP test result into the stored SBC/SBL rules.