Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
December 26, 2006
Patent Application Number
10838969
Date Filed
May 4, 2004
Patent Primary Examiner
Patent abstract
In accordance with the present electronic design automation (EDA) for integrated circuits invention prior to synthesis, dummy elements are added to the library and an internal scan clock pin with no connections is provided. Then the design is synthesized, scan insertion is performed (defining scan chains, inserting chains), and the scan clock is connected to all flip-flops SCLK pins. Finally, the dummy elements are replaced with real gates and clock tree insertion is performed after placing the cell in a layout.
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