US Patent 7164288 Electronic circuit with array of programmable logic cells

An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. The output circuit selects a first output signal OR from the programmable logic units under control of further input signals in the random logic mode and processes second outputs OD from the programmable logic units in parallel in the multi-bit operand mode. The output signal OR does not depend on the carry signal.