US Patent 7164301 State retention power gating latch circuit
Patent 7164301 was granted and assigned to Freescale Semiconductor on January, 2007 by the United States Patent and Trademark Office.
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A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.
US Patent 07164301 State retention power gating latch circuit US Patent 7164301 State retention power gating latch circuit
US Patent 07164301 State retention power gating latch circuit
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