Patent attributes
A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.
