US Patent 7170729 Semiconductor integrated circuit device

A semiconductor integrated circuit of the present invention includes, between a power line 1 and a ground line 2, an NMIS transistor 3 capable of supplying fixed signals with low and high levels to the outside, an NMIS transistor 6 having a source connected to a gate of the NMIS transistor 3, a PMIS transistor 7 having a drain connected to a gate of the NMIS transistor 6, and an ESD protection power clamp circuit 14. If a surge is applied to the power line 1, the ESD protection power clamp circuit 14 is clamped to pass the surge to the ground line. While the surge is passed, the potential of the power line 1 rises to turn on the three transistors 3, 6, and 7. At this time, the NMIS transistor 6 and the PMIS transistor 7 can reduce the gate potential of the NMIS transistor 3 lower than the potential of the power line 1.