Patent attributes
Computer-based design and verification tools provide integrated circuit layouts for use in chromeless phase lithography. A phase-mask design tool assigns feature size descriptors to circuit layout features, and mask features are configured using the feature size descriptors. Feature size descriptors can be assigned based on feature size ranges established based on a mask error function, feature dimensions with respect to a lithographic system resolution limit, or selected properties of aerial image intensity as a function of feature size. Circuit layout features are assigned mask features that include twin phase steps. In addition, circuit layout features associated with selected feature descriptors are assigned sub-resolution assist mask pattern portions or other mask pattern portions based on optical and process corrections.
