Patent attributes
An STM mapping circuit is disclosed having a configuration that includes: a packet length detection circuit for generating byte effectiveness information that indicates whether byte data are effective data or not; routing circuits for generating routing information for rearranging byte data in a prescribed order while using byte effectiveness information to eliminate pad bytes; packet filter circuits for taking in packet data for each logical channel in accordance with channel number signals that indicate which logical channel the packet data belong to; M×M switches for sorting packet data for logical channel in a prescribed order while removing pad bytes in accordance with routing information; and packet memories that hold, for each logical channel, packet data that have been sorted by the M×M switches.
