US Patent 7173993 Method for sampling phase control

Method for sampling phase control for clock and data recovery of a data signal includes sampling a received data signal with a first sampling signal comprising equidistant sampling pulses, minimizing phase deviation between the first sampling signal and the phase of the received data signal to generate an adjusted second sampling signal, and sampling the received data signal with the adjusted second sampling signal to generate sampling data values. The method also includes integrating the sampling data values of the sampled data signal to form a summation value, and altering the phase of sampling pulses of the adjusted second sampling signal until the integrated summation value exceeds a threshold value that can be set.