Patent attributes
A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a substantially small sheet resistance formed at an exhumed surface of a gate stack, wherein the local interconnect electrically couples a gate electrode of the gate stack with an active region of the semiconductor substrate. The method of forming the local interconnect comprises depositing a gate oxide layer over the substrate, a first polysilicon layer over the gate oxide layer, a laterally conducting layer over the polysilicon layer, a second polysilicon layer over the laterally conducting layer, and an insulating layer over the second polysilicon layer. The intermediate structure is then etched so as to form a plurality of gate stacks. A surface of the second polysilicon layer of a gate stack is exhumed so as to allow subsequent formation of the refractory silicide contact at the exhumed surface. A plurality of spacers are formed along the vertical surfaces of the gate stacks and the substrate is selectively doped so as to form active regions within the substrate. A layer of titanium is deposited over the substrate and a silicon source and/or hardmask material layer is deposited over the titanium layer so as to extend between the gate electrode and the active region of the silicon. The mask layer is then patterned in an etching process so that the mask layer defines the extent of the local interconnect structure. The intermediate structure is then exposed to a high temperature N2/NH3 ambient which induces the formation of refractory silicide contacts at the exhumed surface of the polysilicon layer of the gate stack and at the active region of the substrate as well as the formation of refractory nitride (TiN) at the exposed portions of the titanium layer. A selective wet etch follows which removes the exposed unreacted titanium and exposed titanium nitride and leaves behind the local interconnect.
