Patent attributes
An image detection processor has a plurality of image detection processing elements arranged on a plane in a matrix array. Each image detection processing element includes an adder circuit that converts an output of a photo detector into digital signals and can receive the digital signals as an input in a matrix form. The adder circuits for respective rows are connected to form cumulative adders. Series adders are connected in series and respectively receive the outputs of final stages of the cumulative adders of respective rows and cumulatively add these outputs. The digital signals are selectively inputted to the cumulative adders using a row decoder and a column decoder and processed data of an image detected by the photo detectors of the plurality of image detection processing elements are outputted from the last series adder. Processed data from the last series adder are inputted to an edge coordinate detector or a status judgment unit.
