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US Patent 7177458 Reduction of false alarms in PCB inspection

Patent 7177458 was granted and assigned to Orbotech on February, 2007 by the United States Patent and Trademark Office.

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Patent
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Patent attributes

Current Assignee
Orbotech
Orbotech
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
71774580
Patent Inventor Names
Nissim Savareigo0
Nur Arad0
Dan Shalom0
Date of Patent
February 13, 2007
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Patent Application Number
103639820
Date Filed
September 10, 2000
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Patent Citations Received
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US Patent 11935221 User interface for judgment concerning quality classification of displayed arrays of component carriers
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Patent Primary Examiner
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Joseph Mancuso
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Patent abstract

A method for automatically optically inspecting an electrical circuit (12), comprising: acquiring at least one optical image of an electrical circuit (12); generating at least one first inspection image from the at least one image and determining regions of candidate defects (236) therefrom; generating at least one additional inspection image for regions surrounding candidate defects (236), said at least one additional inspection image at least partially including optical information not included in the at least one first inspection image; and determining whether the candidate defect (236) is a specious defect by inspecting the at least one additional inspection image.

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