US Patent 7178005 Efficient implementation of timers in a multithreaded processor
Patent 7178005 was granted and assigned to Sun Microsystems on February, 2007 by the United States Patent and Trademark Office.
All edits
A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator is coupled to convey a read address to the storage device. The read address generator is configured to maintain and increment a first counter. In response to determining the counter does not equal a predetermined value, the mechanism conveys a first read address for use in accessing a count value in the storage device. In response to determining the count equals the predetermined value, the mechanism conveys a second read address for use in accessing a count value in the storage device. The predetermined value is utilized to repeat accesses to a given count value a predetermined number of times.
US Patent 07178005 Efficient implementation of timers in a multithreaded processor US Patent 7178005 Efficient implementation of timers in a multithreaded processor
US Patent 07178005 Efficient implementation of timers in a multithreaded processor
Find more entities like US Patent 7178005 Efficient implementation of timers in a multithreaded processor
