US Patent 7179727 Formation of lattice-tuning semiconductor substrates

A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations (3) extend preferentially across the first SiGe layer between the walls (2) to relieve the strain in the first SiGe layer in directions transverse to the walls (2), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls (2) such that second dislocations form preferentially within the second SiGe layer above the walls (2) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (3). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another. Thus the density of threading dislocations and the surface roughness is greatly reduced, thus enhancing the performance of the virtual substrate by decreasing the disruption of the atomic lattice that can lead to scattering of electrons in the active devices and degradation of the speed of movement of the electrons.