US Patent 7180783 Non-volatile memory devices that include a programming verification function

A non-volatile semiconductor memory device includes a cell array including a plurality of memory cells arranged in a plurality of rows and columns. A page buffer circuit includes a plurality of page buffers corresponding to the plurality of columns, respectively, each page buffer including a first register that is configured to store programming data for a page memory cells and a second register that is configured to store contents of the first register and outside input data. A pass/fail check circuit is configured to generate a programming verification result for the pages of memory cells responsive to the contents of the first registers. A pass/fail check latch circuit is configured to store the programming verification result.