US Patent 7180809 Refresh control circuit of pseudo SRAM

Disclosed herein is a refresh control circuit of a pseudo SRAM. According to the present invention, a single bank select signal for performing a refresh operation on one bank in a period where a chip select signal is enabled, or until a period before a time for reading or writing one data elapses after the chip select signal is disabled is enabled. An all-bank select signal for performing the refresh operation on all the banks in a period after a time for reading or writing one data elapses after the chip select signal is disabled is enabled. Thus, the refresh operation is performed on one bank or all the banks at the same time depending upon the single bank select signal or the all-bank select signal.