Is a
Patent attributes
Current Assignee
0
Patent Jurisdiction
Patent Number
Patent Inventor Names
Tomonori Sekiguchi0
Riichiro Takemura0
Takayuki Kawahara0
Takeshi Sakata0
Kazushige Ayukawa0
Date of Patent
February 27, 2007
0Patent Application Number
112684710
Date Filed
November 8, 2005
0Patent Primary Examiner
Patent abstract
A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.
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