US Patent 7184337 Method for testing an integrated semiconductor memory

A method for testing an integrated semiconductor memory provides for disturbing memory cells arranged along a first word line by a disturbance signal on an adjacent word line. The memory cells along the first word line and bit lines, respectively, connected to them are subsequently connected simultaneously to a common data line via sense amplifiers, respectively, connected to them. The sense amplifiers assess the memory cells burdened by the disturbance signal and the capacitive load of the common data line and, respectively, refresh the disturbed memory state in the memory cells. The memory state refreshed in the memory cells is subsequently assessed in the context of a fast read access.