Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Yutaka Uematsu0
Yoji Nishio0
Yukitoshi Hirose0
Hideki Osaka0
Date of Patent
March 6, 2007
Patent Application Number
10981676
Date Filed
November 5, 2004
Patent Citations Received
Patent Primary Examiner
Patent abstract
The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
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