US Patent 7188061 Simulation monitors based on temporal formulas

A method for design verification includes receiving a software model of a design of a system under evaluation, and providing a property, which is dependent on a specified variable having a predefined range of values. The property applies to all states of the system for any selected value among the values of the variable within the predefined range. The property is processed so as to generate a checker program for detecting a violation of the property. A simulation of the system is then run using the software model together with the checker program.