US Patent 7191255 Transaction layer link down handling for PCI express
Patent 7191255 was granted and assigned to Intel on March, 2007 by the United States Patent and Trademark Office.
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Patent Inventor Names
Kar Leong Wong0
Mikal C. Hunsaker0
Prasanna C. Shah0
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Patent abstract
Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.
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US Patent 07191255 Transaction layer link down handling for PCI express US Patent 7191255 Transaction layer link down handling for PCI express
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Patent Number
071912550
Patent Number
71912550
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Current Assignee
Patent Jurisdiction
Patent Number
071912550
Date of Patent
March 13, 2007
0Patent Application Number
109751320
Date Filed
October 27, 2004
0Official Website
Patent Primary Examiner
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US Patent 07191255 Transaction layer link down handling for PCI express
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07191255
Date of patent
March 13, 2007
Patent application number
10975132
Date Filed
October 27, 2004
Patent primary examiner
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