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US Patent 7193239 Three dimensional structure integrated circuit
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Patent
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Date Filed
July 3, 2003
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Date of Patent
March 20, 2007
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Patent Application Number
10614067
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Patent Citations Received
US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
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US Patent 11804377 Method for preparing a surface for direct-bonding
US Patent 11929347 Mixed exposure for large die
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US Patent 11955445 Metal pads over TSV
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US Patent 12125784 Interconnect structures
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US Patent 11749645 TSV as pad
US Patent 11756880 Interconnect structures
Patent Inventor Names
Glenn J Leedy
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
7193239
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Patent Primary Examiner
Zandra V. Smith
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