US Patent 7197728 Method for setting design margin for LSI

After predicting a relationship between a design margin set against a fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated based on the predicated relationship. The yield is a delay yield obtained by cumulating a signal propagation delay time thereby achieving a probability that a signal propagated through a logic circuit of the LSI is delayed by a given amount of time, and the design margin is a derating factor indicating a ratio between the signal propagation delay time and a standard value of the signal propagation delay time.