Patent attributes
A test arrangement for testing the interconnections of an electronic circuit (100) and a further electronic circuit is provided. A first selection of I/O nodes (120), which are arranged to receive input data in a functional mode of the electronic circuit (100), and which are coupled to a test unit in a test mode of the electronic circuit (100). The test unit has a combinatorial circuit (160) for implementing a multiple-input XOR or XNOR gate. The test unit also provides interconnections between the first selection of I/O nodes (120) and a second selection of I/O nodes (130) via logic gates (141–144). These interconnections increase the interconnect test coverage of the electronic device (100), because the interconnects with the further electronic circuits that are associated with I/O nodes (131–134) become testable as well.
