US Patent 7200058 Semiconductor memory device

A semiconductor memory device includes a memory cell array, in which a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select transistors connected to ends thereof constitute a NAND cell unit, wherein the device has a test mode defined as to detect a read current flowing through the NAND cell unit under the condition of: turning on the first and second select transistors with applying an external voltage to at least one gate of them; simultaneously applying a pass voltage to the entire memory cells in the NAND cell unit to turn on cells without regard to cell data, thereby measuring the property of at least one of the first and second select transistors driven by the external voltage.