US Patent 7200786 Built-in self-analyzer for embedded memory

Methods and apparatus for analyzing memory defects in an embedded memory are described. According to certain embodiments, the analysis can be performed “at-speed” and can be used to analyze multi-bit failures in words of a word-oriented memory. According to some embodiments, the analysis comprises updating a record of column defects not repaired by spare rows as the memory is being tested. The record can be evaluated after a test to determine whether a repair strategy can successfully repair a memory-under-test.