US Patent 7202715 Matched current delay cell and delay locked loop

Matched current delay cells and a delay locked loop based on such cells that may be used for timing data interfaces between semiconductor devices is described. In one embodiment, the delay cell includes a delay cell having a PMOS portion and a NMOS portion, gates of the PMOS portion being coupled to a vp-bias and gates of the NMOS portion being coupled to a vn-bias, the delay cell further being coupled to a reference clock to drive a pulse output of the delay cell, a first bias generation circuit to generate the vn-bias based on a phase comparison of the pulse output to the reference clock, and a second bias generation circuit to generate the vp-bias based on a reference voltage and the vn-bias.