Patent attributes
A power-saving control circuitry of an electronic device is provided. The power-saving control circuitry comprises a power control circuit, an oscillator, a clock pulse generator, a reserve circuit and a multi-enable module. When the electronic device enters a power saving mode, the oscillator stops generating oscillatory timing signals and the clock pulse generator stops generating operational clock signals. Because digital timing signals are generated by either the oscillatory timing signals or the operational clock signals, digital timing signals also stop. Furthermore, power to the flash ROM of the electronic device could be cut off by the signals sent to the oscillator, the clock pulse generator or the multi-enable module from the power control circuit as well.
