Patent attributes
An IFM receiver includes a hybrid for outputting I and Q signals from a received input signal; a first ADC for digitizing the I signal to produce a first digital signal at a sampling rate of 1/τ, and a second ADC for digitizing the Q signal to produce a second digital signal at the same sampling rate. A processor is configured to (a) delay the first and second digital signals by at least one sample time of τ, (b) count the number of samples produced having predetermined phase shifts, and (c) determine the frequency of the received input signal, based on the number of samples having the predetermined phase shifts. The first and second ADCs are each 1-bit analog-to-digital converters. The predetermined phase shifts of 0°, 90°, −90° and 180° are counted by the processor over a predetermined time interval.
