Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
May 8, 2007
Patent Application Number
11187981
Date Filed
July 25, 2005
Patent Primary Examiner
Patent abstract
In the assembly of a semiconductor device, improvement in the reliability of flip chip bonding is aimed at. By forming a dummy terminal in the end portion of the row of a plurality of terminals for a flip chip in the package substrate, the flow of flux or solder can be suppressed with the dummy terminal, and a solder layer can be formed on the plurality of terminals for a flip chip. Thereby, the thickness of the solder layer formed on each terminal for a flip chip can fully be secured, without making solder adhere to the wire connection terminal closely formed to the terminal for a flip chip. As a result, improvement in the reliability of flip chip bonding can be aimed at.
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