US Patent 7217644 Method of manufacturing MOS devices with reduced fringing capacitance
Patent 7217644 was granted and assigned to Intel on May, 2007 by the United States Patent and Trademark Office.
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Patent Inventor Names
Brian Doyle0
Jack Kavalieros0
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Patent abstract
An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.
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US Patent 07217644 Method of manufacturing MOS devices with reduced fringing capacitance US Patent 7217644 Method of manufacturing MOS devices with reduced fringing capacitance
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Patent Number
072176440
Patent Number
72176440
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Current Assignee
Patent Jurisdiction
Patent Number
072176440
Date of Patent
May 15, 2007
0Patent Application Number
108972910
Date Filed
July 21, 2004
0Official Website
Patent Primary Examiner
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US Patent 07217644 Method of manufacturing MOS devices with reduced fringing capacitance
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07217644
Date of patent
May 15, 2007
Patent application number
10897291
Date Filed
July 21, 2004
Patent primary examiner
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