Patent attributes
The PL signal of a PL portion is multiplied by gain factor βc in a multiplier(109) and the data of a data portion is multiplied by gain factor βd in a multiplier(110). These gain factors βc and βd are controlled in a weight controlling circuit (112). The PL signal and data thus multiplied by gain factors are added in an adder (111) and become an added PL signal. This added PL signal is output to a delay profile generation circuit (113). In the delay profile generation circuit (113), a delay profile is generated using the added PL signal. The delay profile is output to a path selection circuit (104) where path search is performed, and the information of selected reception timings are output to a RAKE combining circuit (105) and a channel estimation circuit (115). By this means, iterative path search and channel estimation can be performed with accuracy even when receiving signals where channels of different transmission power ratios are multiplexed.
