US Patent 7219188 Segmented content addressable memory array and priority encoder

A CAM includes a plurality of CAM blocks, each including an array of CAM cells divided into a plurality of segments, each array segment for storing a number of data values that are assigned the same priority, a plurality of block priority circuits, each having inputs to receive match signals from a corresponding CAM block and having outputs to generate a block index and priority of a matching data value in the corresponding CAM block assigned the highest priority, and a global priority and index circuit having inputs to receive the block indexes and associated priorities from the block priority circuits, and having an output to generate a device index and associated priority of the highest priority matching value.