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US Patent 7219422 Fabrication method of semiconductor integrated circuit device

Patent 7219422 was granted and assigned to Renesas Technology Corp on May, 2007 by the United States Patent and Trademark Office.

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Current Assignee
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7219422
Date of Patent
May 22, 2007
Patent Application Number
10765917
Date Filed
January 29, 2004
Patent Primary Examiner
‌
Paul D. Kim
Patent abstract

The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

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