US Patent 7225116 Method for eliminating routing congestion in an IC layout

Patent 7225116 was granted and assigned to Cadence Design Systems on May, 2007 by the United States Patent and Trademark Office.

Overview Structured Data Issues Contributors Activity

Is a

Patent

Patent attributes

Current Assignee

Cadence Design Systems

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

72251160

Patent Inventor Names

Ywh-Pyng Harn0

Date of Patent

May 29, 2007

Patent Application Number

102252150

Date Filed

August 20, 2002

Patent Primary Examiner

‌

Kamini Shah

Patent abstract

The invention relates to a method for eliminating routing congestion in an integrated circuit (IC) layout defined by a placement plan indicating a position within the layout of each cell forming the IC and routing plan describing routes followed by nets interconnecting the cells. Routing congestion is eliminated by estimating routing congestion in various areas of the layout and relocating each cell to least routing congested areas of the layout for which cell relocation results in a reduction in the total lengths of the nets connected to the cell that exceeds a predetermined minimum reduction.

Timeline

No Timeline data yet.

Further Resources

Title

Author

Link

Type

Date

No Further Resources data yet.

References

Find more entities like US Patent 7225116 Method for eliminating routing congestion in an IC layout

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.

Open Query Tool

Access by API