US Patent 7228513 Circuit operation verification device and method

A circuit verification device includes emulators to which circuit portions obtained by dividing the circuit are implemented. The emulators communicate with each other through a bus to verify the functional operation of the circuit. The circuit is divided based on a communication occurrence pattern between circuit units so that the number of communications occurring between circuit portions is minimized. The input signals of the bus are preferably arranged in the bus address space in descending order of a signal change rate, and a burst transfer may be utilized. Through paths within the circuit being verified are searched, and a plurality of circuit units is divided so as to minimize the number of through paths among the circuit portions.