US Patent 7231539 Reset circuit for resetting two clock domains

A reset circuit for resetting two clock domains resets the two clock domains synchronously with a first clock signal in response to assertion of a system reset. It then de-asserts the resetting of a first of the clock domains in synchronization with the first clock signal, and de-asserts the resetting of a second of the clock domains in synchronization with a second clock signal so that the second clock domain is not operative until after the second clock signal is running.