US Patent 7232692 Photo-imaged stress management layer for semiconductor devices
Patent 7232692 was granted and assigned to Finisar on June, 2007 by the United States Patent and Trademark Office.
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Patent Inventor Names
James Guenter0
Jose Aizpuru0
Robert Hawthorne0
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Patent abstract
A photo-imaged stress management layer for a semiconductor device is described. The stress management layer is located on an outer surface of a semiconductor device and may be patterned to address certain stress compensation requirements of the semiconductor device. The stress management layer may be manufactured onto the semiconductor device using a photolithographic procedure that allows both simple and complex patterns to be realized.
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US Patent 07232692 Photo-imaged stress management layer for semiconductor devices US Patent 7232692 Photo-imaged stress management layer for semiconductor devices
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Patent Number
07232692
Patent Number
7232692
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Official Website
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US Patent 07232692 Photo-imaged stress management layer for semiconductor devices
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Is a
Current assignee
Patent jurisdiction
Patent number
07232692
Date of patent
June 19, 2007
Patent application number
11071940
Date Filed
March 4, 2005
Patent primary examiner
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