Patent attributes
A delay-locked loop circuit receiving an input clock signal and generating an output clock signal whose delay is locked to the input clock includes a voltage controlled delay line (VCDL), a multiplexer, a phase detection control loop and a phase selection control loop. The VCDL generates a set of multi-phase delayed clock signals. The multiplexer selects one of the delayed clock signals as the output clock signal based on a select signal. The phase detection control loop measures the phase difference between the input and output clock signals and generate a control voltage for driving the VCDL. The phase selection control loop measures the control voltage and generates the select signal based on the control voltage, causing the multiplexer to select a delayed clock signal with increased or decreased amount of phase delay relative to the currently selected delayed clock signal or to hold the currently selected delayed clock signal.
