US Patent 7236557 Counter-based clock multiplier circuits and methods

Clock multiplier circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is then divided and the divided values are combined to provide counter stop values representing the numbers of counts in various fractions of the input clock period. A second counter counts from an initial value starting from a first edge of the input clock, and the count is compared in turn to the each of the counter stop values. When the value in the second counter matches one of the counter stop values, a pulse is generated on the output clock signal. Thus, the second counter generates a series of pulses at predetermined times in the input clock period.