Patent attributes
A thin film transistor array panel according to the present invention includes a first wire, a second wire, and a pixel electrode. The first wire is formed on an insulating substrate and is used as a gate line or a storage capacitor electrode. The second wire overlaps the first wire via a gate insulating layer and is used as a storage capacitor conductor or a drain electrode. The pixel electrode is formed on a passivation layer covering the second wire and is connected to the second wire through a contact hole of a second insulating layer. In order to secure aperture ratio of the pixel and to block light leakage, distances between the boundaries of the contact hole at the place where alignment treatment or rubbing ends and the boundaries of the first wire or the second wire adjacent thereto and located outside the boundaries of the contact hole are designed to be wider than those between the boundaries of the contact hole at the other places and the boundaries of the first wire or the second wire.
