US Patent 7245540 Controller for delay locked loop circuits

A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.