Patent attributes
A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The oxide defined (OD) area is formed on an insulating layer, extending across at least two neighboring SRAM cell areas for construction of a passing gate transistor and a pull-down transistor used in an SRAM cell. The strapping cell area is interposed between the SRAM cell areas, in which a strapping cell is constructed for connecting the OD area to a fixed potential, thereby preventing bodies of the passing gate transistor and the pull-down transistor constructed on the OD area from floating.
