US Patent 7254505 Method and apparatus for calibrating delay lines
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A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse signal by a selected time delay. A feedback loop of the DL circuit feeds the delayed pulse signal output from the delay line back to the input of the pulse generating circuit. Receipt of an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal. The delayed pulse signal output from the delay line can be input to a counter that generates a counter value that is based on the period of oscillation of the delayed pulse signal.
US Patent 07254505 Method and apparatus for calibrating delay lines US Patent 7254505 Method and apparatus for calibrating delay lines
US Patent 07254505 Method and apparatus for calibrating delay lines
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