Patent attributes
A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60Ω) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion. A plurality of contacts to the substrate connects to the resistor so that the voltage drop is uniformly impressed on the substrate to ensure uniform turn-on of the elongated transistor for uniform pulse discharge.
